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MCP2030
5.26
Factory Calibration
5.28
Demodulator
The device is calibrated during probe test to reduce the
device-to-device variation in standby current, internal
timing and sensitivity, as well as channel-to-channel
sensitivity variation.
5.27 De-Q’ing of Antenna Circuit
When the transponder is close to the base station, the
transponder coil may develop coil voltage higher than
V DE_Q . This condition is called “near field”. The device
detects the strong near field signal through the AGC
control, and de-Q’ing the antenna circuit to reduce the
input signal amplitude.
Input at LC input pins
Full-wave Rectifier output
Demodulated LFDATA output
T DR
The demodulator recovers the modulation data from
the received signal, containing carrier plus data, by
appropriate envelope detection. The demodulator has
a fast rise (charge) time (T DR ) and a fall time (T DF )
appropriate to an envelope of input signal (see
Section 1.0 “Electrical Specifications” for T DR and
T DF specifications). The demodulator contains the
full-wave rectifier, low-pass filter, peak detector and
data slicer.
T DF
FIGURE 5-6:
Demodulator Charge and Discharge.
5.29
Power-On Reset
For a clean data output or to save operating power, the
This circuit remains in a Reset state until a sufficient
supply voltage is applied. The Reset releases when the
supply is sufficient for correct device operation,
nominally V POR .
The Configuration registers are all cleared on a Power-
on Reset. As the Configuration registers are protected
by odd row and column parity, the ALERT pin will be
pulled down – indicating to the external microcontroller
section that the configuration memory is cleared and
requires new programming.
input channels can be individually enabled or disabled.
If more than one channel is enabled, the output is the
sum of each output of all enabled channels. There will
be no valid output if all three channels are disabled.
When the demodulated output is selected, the output is
available in two different conditions depending on how
the options of Configuration Register 0 (Register 5-1)
are set: Output Enable Filter is disabled or enabled.
See Section 2.0 “Typical Performance Curves” for
various demodulated data output.
Related Configuration register bits:
5.30
LFDATA Output Selection
? Configuration Register 1 (Register 5-2),
DATOUT <8:7>:
The LFDATA output can be configured to pass the
bit 8 bit 7
Demodulator output, Received Signal Strength Indi-
cator (RSSI) output, or Carrier Clock (CCLK). See
Configuration Register 1 (Register 5-2) for more
details.
0
0
1
0 : Demodulator Output
1 : Carrier Clock Output
0 : RSSI Output
5.30.1
DEMODULATOR OUTPUT
0
1 : RSSI Output
The demodulator output is the default configuration of
the output selection. This is the output of an envelope
detection circuit. See Figure 5-6 for the demodulator
output.
? 2005 Microchip Technology Inc.
? Configuration Register 0 (Register 5-1): all bits
DS21981A-page 43
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